Intel MAX V 5M40Z CPLD Field-programmable gate array (FPGA)

Internal Oscillator
The internal oscillator is used to meet the clocking requirements of many designs and eliminate the requirement for an external clock circuitry.

Fast Power-on Reset
Fast reset of the entire design to an initial and well-known state after the power supply is detected.

Boundary-scan JTAG
Testing that isolates a device's internal circuitry from its I/O circuitry.

JTAG ISP
In-System Programmability via JTAG interface.

Fast Input Registers
Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up
Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator
Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP
Can program the supported device while the device is still in operation.