XS1 Event-Driven Processor. An XS1 combines a number of XCore™ processors, each with its own memory, on a single chip. The programmable processors are general purpose in the sense that they can execute languages such as C; they also have direct support for concurrent processing (multi-threading), communication and input-output. A high-performance switch supports communication between the processors, and inter-chip XMOS Links are provided so that systems can easily be constructed from multiple chips. The XS1 products are intended to make it practical to use software to perform many functions which would normally be done by hardware; an important example is interfacing and input-output controllers. Each XCore processor provides the following resources: 32-bit processor providing up to 500MIPS Eight hardware threads and 32 channel ends Ten timers and six clock blocks Four XMOS Links 64KBytes SRAM and 8KBytes OTP memory More information:  | | Package Type: | QFN | Pin Count: | 124 |
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