Clock Drivers & Distribution (250 items)

The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept mos...

Logic Function = Clock Buffer Number of Clock Inputs = 5 Package Type = TSSOP Pin Count = 20

Logic Function = Clock Buffer Input Signal Type = LVPECL Number of Clock Inputs = 2 Package Type = SOIC Pin Count = 8

The Renesas Electronics 853S011B is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011B is characterized to operate from either a 2.5V or a 3.3V pow...

Logic Family = LVDS Logic Function = Clock Buffer Input Signal Type = LVDS Number of Clock Inputs = 2 Package Type = SOIC Pin Count = 24

The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is cha...

The Renesas Electronics 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data sign...

Logic Family = LVPECL Logic Function = Clock Buffer Input Signal Type = LVPECL Number of Clock Inputs = 4 Package Type = LFCSP Pin Count = 28

The Renesas Electronics 8T49N241 has one fractional-feedback PLL that can be used as a jitter attenuator and frequency translator. It is equipped with one integer and three fractional output divide...

Mounting Type = Surface Mount Package Type = VFQFN Pin Count = 40

The Renesas Electronics 8T49N241 has one fractional-feedback PLL that can be used as a jitter attenuator and frequency translator. It is equipped with one integer and three fractional output divide...

Mounting Type = Surface Mount Package Type = VFQFN Pin Count = 40

Logic Family = HCSL, LVDS Logic Function = Translator Input Signal Type = HCSL, LVDS, LVPECL Output Logic Level = HCSL, LVDS, LVPECL Operation Mode = Differential, Single Ended Number of Clock Inpu...

Logic Family = HCSL, LVDS Logic Function = Translator Input Signal Type = HCSL, LVDS, LVPECL Output Logic Level = HCSL, LVDS, LVPECL Operation Mode = Differential, Single Ended Number of Clock Inpu...

Logic Family = LVDS, LVPECL Logic Function = Clock Driver Input Signal Type = LVDS, LVPECL Operation Mode = Differential Number of Clock Inputs = 2 Package Type = VFQFPN Pin Count = 88